1. Field of the Invention
The present invention relates generally to dielectric layers employed within microelectronic fabrications. More particularly, the present invention relates to delamination resistant multi-layer dielectric layers for passivating patterned conductor layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly significant within the art of microelectronic fabrication to form microelectronic fabrications with enhanced levels of stability and reliability, since incident to forming microelectronic fabrications with decreased dimensions there is often enhanced internal stresses within a microelectronic fabrication such that the microelectronic fabrication is formed with diminished stability and reliability.
It is thus towards the goal of forming within the art of microelectronic fabrication microelectronic fabrications with enhanced stability and reliability that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming, in general, microelectronic fabrications, or more particularly, various microelectronic layers within microelectronic fabrications, with enhanced or desirable properties.
For example, Cathey et al., in U.S. Pat. No. 5,185,058, discloses a method for forming a patterned metal containing conductor layer within a microelectronic fabrication, where the patterned metal containing conductor layer is formed with a vertical sidewall profile or a positively tapered sidewall profile, rather than a negatively tapered sidewall profile or an otherwise undercut sidewall profile. The method realizes the foregoing object by employing when forming the patterned metal containing conductor layer from a corresponding blanket metal containing conductor layer while employing a plasma etch method an etchant gas composition which includes in addition to an etchant gas a coating gas, where the coating gas comprises a gaseous oxide of carbon, such as carbon monoxide or carbon dioxide, along with a silicon containing compound, such as silicon tetrafluoride, silicon tetrachloride or silicon tetrabromide.
In addition, Tabara, in U.S. Pat. No. 5,399,527 and U.S. Pat. No. 5,519,254, discloses a multi-layer aluminum containing conductor layer structure fabricated within a microelectronic fabrication, and a method for forming the multi-layer aluminum containing conductor layer structure fabricated within the microelectronic fabrication, where a capping layer within the multi-layer aluminum containing conductor layer structure fabricated within the microelectronic fabrication is less susceptible to thinning incident to etching, while employing a plasma etch method, a via through a silicon containing dielectric layer which passivates the multilayer aluminum containing conductor layer when etching the via to reach the multi-layer aluminum containing conductor layer. The method realizes the foregoing object by incorporating into the capping layer, which is not otherwise formed of an aluminum containing conductor material, a conductor material, such as aluminum, which suppresses etching of the capping layer within the plasma etch method.
Further, Huang et al., in U.S. Pat. No. 5,639,345, discloses a method for forming, with improved cross-substrate thickness uniformity, a reactive ion etch (RIE) etchback planarized spin-on-glass (SOG) planarizing layer within a microelectronic fabrication. The method realizes the foregoing object by employing when forming the reactive ion etch (RE) etchback planarized spin-on-glass (SOG) planarizing layer within the microelectronic fabrication, in sequence: (1) a first reactive ion etch (RIE) method having a lower etch rate for a portion of a spin-on-glass (SOG) planarizing layer formed over the center of a substrate employed within the microelectronic fabrication with respect to the periphery of the substrate employed within the microelectronic fabrication, followed by; (2) a second reactive ion etch (RE) method having a higher etch rate for the portion of the spin-on-glass (SOG) planarizing layer formed over the center of the substrate employed within the microelectronic fabrication with respect to the periphery of the substrate employed within the microelectronic fabrication.
Still further, Nishitani et al., in U.S. Pat. No. 5,670,421, discloses a method for selectively forming within a via through a dielectric layer within a microelectronic fabrication, which via accesses a conductor layer within the microelectronic fabrication, a chemical vapor deposited (CVD) tungsten layer with high selectivity even when the surface of the conductor layer exposed within the via has been subject to a pre-cleaning to assure optimal contact with the chemical vapor deposited (CVD) tungsten layer. The method realizes the foregoing object by employing, either concurrent with or subsequent to pre-cleaning of the surface of the conductor layer, a stabilizing treatment for the surface of the dielectric layer which is otherwise activated incident to pre-cleaning of the surface of the conductor layer exposed within the via.
Yet still further, Yu et al., in U.S. Pat. No. 5,702,980, discloses a method for forming within a microelectronic fabrication a spin-on-glass (SOG) sandwich composite planarizing dielectric layer construction within attenuated defect formation within an upper lying capping dielectric layer within the spin-on-glass (SOG) sandwich composite planarizing dielectric layer construction. The method employs when forming the spin-on-glass (SOG) sandwich composite planarizing dielectric layer construction a bilayer upper lying capping dielectric layer comprising: (1) a first upper lying capping dielectric layer formed contacting at least in part portions of a spin-on-glass (SOG) layer planarizing layer, where the first upper lying capping dielectric layer is formed of a first silicon oxide dielectric material deposited employing a plasma enhanced chemical vapor deposition (PECVD) method employing silane as a silicon source materials and oxygen as an oxidant source material; and (2) a second upper lying capping dielectric layer formed upon the first upper lying capping dielectric layer, where the second upper lying capping dielectric layer is formed of a second silicon oxide dielectric material deposited employing a plasma enhanced chemical vapor deposition (PECVD) method employing tetraethylorthosilicate as a silicon source material.
Finally, Bersin et al., in U.S. Pat. No. 5,882,489, discloses a method for stripping from over a substrate employed within a microelectronic fabrication organic residues and inorganic residues, such as obtained from photoresist materials, without use of acids or organic solvents when stripping the organic residues and inorganic residues. To realize the foregoing object, the method first employs an oxygen plasma ashing to strip organic residues, followed by, in either order: (1) a rinsing within deionized water to remove any remaining soluble organic residues; and (2) a sputtering within an argon ion sputtering method to remove inorganic residues.
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed to form microelectronic fabrications with enhanced stability and reliability.
It is towards the foregoing object that the present invention is directed.